Compact modeling of 0.35 μm SOI CMOS technology node for 4 K DC operation using Verilog-A
| Autor: | Akturk, A., Peckerar, M., Eng, K., Hamlet, J., Potbhare, S., Longoria, E., Young, R., Gurrieri, T., Carroll, M.S., Goldsman, N. |
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| Zdroj: | In Microelectronic Engineering 2010 87(12):2518-2524 |
| Databáze: | ScienceDirect |
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