A formal model for proving hardware timing properties and identifying timing channels
| Autor: | Qin, Maoyuan, Wang, Xinmu, Mao, Baolei, Mu, Dejun, Hu, Wei |
|---|---|
| Zdroj: | In Integration May 2020 72:123-133 |
| Databáze: | ScienceDirect |
| Externí odkaz: |
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| Autor: | Qin, Maoyuan, Wang, Xinmu, Mao, Baolei, Mu, Dejun, Hu, Wei |
|---|---|
| Zdroj: | In Integration May 2020 72:123-133 |
| Databáze: | ScienceDirect |
| Externí odkaz: |
|
Full Text from ScienceDirect