Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework

Autor: Garzón, Esteban, De Rose, Raffaele, Crupi, Felice, Trojman, Lionel, Finocchio, Giovanni, Carpentieri, Mario, Lanuzza, Marco
Zdroj: In Integration March 2020 71:56-69
Databáze: ScienceDirect