AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation
| Autor: | Lourenço, Nuno, Martins, Ricardo, Canelas, António, Póvoa, Ricardo, Horta, Nuno |
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| Zdroj: | In Integration, the VLSI Journal September 2016 55:316-329 |
| Databáze: | ScienceDirect |
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