Leakage reduction in dual mode logic through gated leakage transistors
| Autor: | Yadav, Neetika, Pandey, Neeta, Nand, Deva |
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| Zdroj: | In Microprocessors and Microsystems July 2021 84 |
| Databáze: | ScienceDirect |
| Externí odkaz: |
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| Autor: | Yadav, Neetika, Pandey, Neeta, Nand, Deva |
|---|---|
| Zdroj: | In Microprocessors and Microsystems July 2021 84 |
| Databáze: | ScienceDirect |
| Externí odkaz: |
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Full Text from ScienceDirect