Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview
| Autor: | Vallero, A., Tselonis, S., Foutris, N., Kaliorakis, M., Kooli, M., Savino, A., Politano, G., Bosio, A., Di Natale, G., Gizopoulos, D., Di Carlo, S. |
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| Zdroj: | In Microprocessors and Microsystems November 2015 39(8):1204-1214 |
| Databáze: | ScienceDirect |
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Full Text from ScienceDirect