Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
| Autor: | Fenouillet-Beranger, C., Perreau, P., Benoist, T., Richier, C., Haendler, S., Pradelle, J., Bustos, J., Brun, P., Tosti, L., Weber, O., Andrieu, F., Orlando, B., Pellissier-Tanon, D., Abbate, F., Richard, C., Beneyton, R., Gregoire, M., Ducote, J., Gouraud, P., Margain, A., Borowiak, C., Bianchini, R., Planes, N., Gourvest, E., Bourdelle, K.K., Nguyen, B.Y., Poiroux, T., Skotnicki, T., Faynot, O., Boeuf, F. |
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| Zdroj: | In Solid State Electronics October 2013 88:15-20 |
| Databáze: | ScienceDirect |
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Full Text from ScienceDirect