Managing annealing pattern effects in 45 nm low power CMOS technology
| Autor: | Morin, P., Cacho, F., Beneyton, R., Dumont, B., Colin, A., Bono, H., Villaret, A., Josse, E., Bianchini, R. |
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| Zdroj: | In Solid State Electronics 2010 54(9):897-902 |
| Databáze: | ScienceDirect |
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