Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level
Autor: | Valasa, Sresta, Kotha, Venkata Ramakrishna, Vadthiya, Narendar |
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Zdroj: | In Microelectronics Reliability September 2024 160 |
Databáze: | ScienceDirect |
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