Effects of low gate bias annealing in NBT stressed p-channel power VDMOSFETs

Autor: Manić, I., Danković, D., Djorić-Veljković, S., Davidović, V., Golubović, S., Stojadinović, N.
Zdroj: In Microelectronics Reliability 2009 49(9):1003-1007
Databáze: ScienceDirect