Gated Vernier delay line time integrator with applications in [formula omitted] time-to-digital converter

Autor:	Parekh, Parth, Yuan, Fei, Zhou, Yushi
Zdroj:	In Microelectronics Journal January 2022 119
Databáze:	ScienceDirect
Externí odkaz:	Zobrazit plný text záznamu Full Text from ScienceDirect