Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors
| Autor: | Zajac, Piotr, Galicia, Melvin, Maj, Cezary, Napieralski, Andrzej |
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| Zdroj: | In Microelectronics Journal June 2016 52:40-48 |
| Databáze: | ScienceDirect |
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