LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier
| Autor: | Nayan, Nazrul Anuar, Takahashi, Yasuhiro, Sekine, Toshikazu |
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| Zdroj: | In Microelectronics Journal April 2012 43(4):244-249 |
| Databáze: | ScienceDirect |
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Full Text from ScienceDirect