| Autor: |
Xiaoyuan Wang, Xinrui Zhang, Chuantao Dong, Shimul Kanti Nath, Herbert Ho-Ching Iu |
| Jazyk: |
angličtina |
| Rok vydání: |
2023 |
| Předmět: |
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| Zdroj: |
Micromachines, Vol 14, Iss 10, p 1895 (2023) |
| Druh dokumentu: |
article |
| ISSN: |
2072-666X |
| DOI: |
10.3390/mi14101895 |
| Popis: |
This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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