| Autor: |
Yu-Pei Liang, Hao Chen, Ching-Che Chung |
| Jazyk: |
angličtina |
| Rok vydání: |
2024 |
| Předmět: |
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| Zdroj: |
Sensors, Vol 24, Iss 23, p 7831 (2024) |
| Druh dokumentu: |
article |
| ISSN: |
1424-8220 |
| DOI: |
10.3390/s24237831 |
| Popis: |
This paper presents a hardware implementation of a one-dimensional convolutional neural network using depthwise separable convolution (DSC) on the VC707 FPGA development board. The design processes the one-dimensional rolling bearing current signal dataset provided by Paderborn University (PU), employing minimal preprocessing to maximize the comprehensiveness of feature extraction. To address the high parameter demands commonly associated with convolutional neural networks (CNNs), the model incorporates DSC, significantly reducing computational complexity and parameter load. Additionally, the DoReFa-Net quantization method is applied to compress network parameters and activation function outputs, thereby minimizing memory usage. The quantized DSC model requires approximately 22 KB of storage and performs 1,203,128 floating-point operations in total. The implementation achieves a power consumption of 527 mW at a clock frequency of 50 MHz, while delivering a fault diagnosis accuracy of 96.12%. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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