| Autor: |
Shogo Semba, Hiroshi Saito |
| Jazyk: |
angličtina |
| Rok vydání: |
2023 |
| Předmět: |
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| Zdroj: |
IEEE Access, Vol 11, Pp 13408-13420 (2023) |
| Druh dokumentu: |
article |
| ISSN: |
2169-3536 |
| DOI: |
10.1109/ACCESS.2023.3243224 |
| Popis: |
In this paper, we propose a design support tool set for interface circuits between synchronous and asynchronous modules. To facilitate the design of interface circuits between synchronous and asynchronous modules, the proposed tool set generates interface circuits and design constraints based on a predefined communication scheme. In addition, the proposed tool set performs timing verification and delay adjustment to guarantee the operations of the generated interface circuits. In the experiment, we evaluated the latency and overhead of the generated interface circuits. The latency and handshake overhead of the interface circuits generated by the proposed tool set depend on the cycle time of the receiver module. In addition, we designed a system which consists of a synchronous RISC-V processor and an asynchronous multilayer perceptron (MLP) circuit using the proposed tool set. The energy consumption of the system was reduced by 34.0% compared with a system which uses a synchronous MLP circuit. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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