| Autor: |
Zdravko Todorov, Danijela Efnusheva, Ana Cholakoska, Marija Kalendar |
| Jazyk: |
angličtina |
| Rok vydání: |
2021 |
| Předmět: |
|
| Zdroj: |
Proceedings of the International Conference on Applied Innovations in IT, Vol 9, Iss 1, Pp 1-6 (2021) |
| Druh dokumentu: |
article |
| ISSN: |
2199-8876 |
| DOI: |
10.25673/36577 |
| Popis: |
With the increasing number of Internet devices, the emergence of IoT, 5G and the increased traffic between the devices, the IPv6 is complementing IPv4. As IPv6 is becoming the protocol of choice by the new technologies, in order to accommodate for the features demanded by these technologies it is necessary to have high speed and low latency between the connected nodes. This paper introduces a hardwired IPv6 FPGA node, which processes IPv6 packets and is focused on high-speed transmission. Although, the code is written VHDL, it is written in a way which enables the user to easily add new features and implement new extension headers. The implementation of this IPv6 header processor is done on a Virtex7 VC709 FPGA development board. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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