| Popis: |
Complementary Metal Oxide Silicon (CMOS) technology faces a major concern in power dissipation due to the scale-down of technology nodes to the nanoscale. To, resolve this problem, logic-in-memory (LIM) structures are researched as a solution. A spintronics device called magnetic tunnel junction (MTJ) uses less static power than CMOS technology. To improve the energy efficiency of LIM structures, spin-transfer torque based magnetic tunnel junction (STT-MTJ) and CMOS are used to design digital circuits. In this paper, the design of hybrid AND/NAND, OR/NOR, and XOR/XNOR logic gate are done by exploring two proposed LIM designs namely LIM1 based on a pre-charge sense amplifier (PCSA) and LIM2 based on a modified version of PCSA (M-PCSA)using the Cadence simulator. This work considers the incorporation of separated transistor logic into the LIM structure to provide separate read and write paths.The results are compared in respect of delay, power, gate count and energy consumption.The proposed LIM1 and LIM2-based AND/NAND, OR/NOR and XOR/XNOR design shows 47.5%, 49.6%, 41.9% and 59.3%, 60.7%, 55.7% lower energy consumption respectively compared to the existing CMOS-based designs. This paper exhibits the design of energy efficient hybrid MTJ/CMOS structures using optimized read/write circuitry and it is appropriate for IoT applications. |
