| Autor: |
V. R. Tirumalasetty, S. Avireni |
| Jazyk: |
angličtina |
| Rok vydání: |
2012 |
| Předmět: |
|
| Zdroj: |
Radioengineering, Vol 21, Iss 4, Pp 1279-1286 (2012) |
| Druh dokumentu: |
article |
| ISSN: |
1210-2512 |
| Popis: |
Full adder is an essential component for the design and development of all types of processors like digital signal processors (DSP), microprocessors etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. In this paper, we proposed two modified level restorers using current sink and current source inverter structures for branch-based logic and pass-transistor (BBL-PT) full adder [1]. In BBL-PT full adder, there lies a drawback i.e. voltage step existence that could be eliminated in the proposed logics by using the current sink inverter and current source inverter structures. The proposed full adders are compared with the two standard and well-known logic styles, i.e. conventional static CMOS logic and Complementary Pass transistor Logic (CPL), demonstrated the good delay performance. The implementation of 8-bit ripple carry adder based on proposed full adders are finally demonstrated. The CPL 8-bit RCA and as well as the proposed ones is having better delay performance than the static CMOS and BBL-PT 8-bit RCA. The performance of the proposed BBL-PT cell with current sink & current source inverter structures are examined using PSPICE and the model parameters of a 0.13 µm CMOS process. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
|
