Autor: |
Maosong Xie, Yueyang Jia, Chen Nie, Zuheng Liu, Alvin Tang, Shiquan Fan, Xiaoyao Liang, Li Jiang, Zhezhi He, Rui Yang |
Jazyk: |
angličtina |
Rok vydání: |
2023 |
Předmět: |
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Zdroj: |
Nature Communications, Vol 14, Iss 1, Pp 1-11 (2023) |
Druh dokumentu: |
article |
ISSN: |
2041-1723 |
DOI: |
10.1038/s41467-023-41736-2 |
Popis: |
Abstract Emerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS2) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems. |
Databáze: |
Directory of Open Access Journals |
Externí odkaz: |
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