| Autor: |
Jonathan F. Bolus, Benton H. Calhoun, Travis N. Blalock |
| Jazyk: |
angličtina |
| Rok vydání: |
2014 |
| Předmět: |
|
| Zdroj: |
Journal of Low Power Electronics and Applications, Vol 4, Iss 3, Pp 252-267 (2014) |
| Druh dokumentu: |
article |
| ISSN: |
2079-9268 |
| DOI: |
10.3390/jlpea4030252 |
| Popis: |
A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ΔVT between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows for the characterization of ID bit reliability by characterizing ΔVT . An addressing scheme is also presented that allows for reliable on-chip identification of ICs in the presence of unreliable ID bits. An example implementation is presented that can address 1000 unique ICs, composed of 31 ID bits and having an error rate less than 10-6, with up to 21 unreliable bits. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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