| Autor: |
Yu-Lun Hsu, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang |
| Jazyk: |
angličtina |
| Rok vydání: |
2024 |
| Předmět: |
|
| Zdroj: |
IEEE Open Journal of Circuits and Systems, Vol 5, Pp 189-198 (2024) |
| Druh dokumentu: |
article |
| ISSN: |
2644-1225 |
| DOI: |
10.1109/OJCAS.2024.3363043 |
| Popis: |
The trade-off between decoding performance and hardware costs has been a long-standing challenge in Low-Density Parity Check (LDPC) decoding. Based on model-driven methodology, the Neural Network-Aided Variable Weight Min-Sum (NN-aided vwMS) algorithm is proposed to address this dilemma in this paper. Not only eliminating the second minimum value in the check node update process for reducing hardware complexity, our approach featuring a fast-convergent shuffled scheduling method proposed to enhance convergence speed can also maintain similar decoding performance as compared to the traditional normalized min-sum algorithm. Different from existing model-driven methodologies only suitable for short codes, a Globally-Coupled Like (GC-like) LDPC code construction is presented to enable efficient training with simplified neural networks for longer LDPC codes. To demonstrate the capability of the NN-aided vwMS algorithm with the fast-convergent shuffled scheduling method, a GC-like (9126,8197) LDPC decoder is implemented for NAND flash applications, achieving a 6.56 Gbps throughput with a core area of $0.58~mm^{2}$ under the 40-nm CMOS TSMC process, and average power consumption of 288 mW under the frame error rate of $2.64 \times 10^{-5}$ at 4.5dB. Our decoder architecture achieves a superior normalized throughput-to-area ratio of $11.31~Gbps/mm^{2}$ , demonstrating a 2.4x improvement among previous works. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
|
