Autor: |
Naheem Olakunle Adesina, Ashok Srivastava |
Jazyk: |
angličtina |
Rok vydání: |
2019 |
Předmět: |
|
Zdroj: |
Journal of Low Power Electronics and Applications, Vol 9, Iss 3, p 24 (2019) |
Druh dokumentu: |
article |
ISSN: |
2079-9268 |
DOI: |
10.3390/jlpea9030024 |
Popis: |
The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741−994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations. |
Databáze: |
Directory of Open Access Journals |
Externí odkaz: |
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