| Autor: |
Karam Cho, Sumeet Kumar Gupta |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
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| Zdroj: |
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 8, Iss 2, Pp 157-165 (2022) |
| Druh dokumentu: |
article |
| ISSN: |
2329-9231 |
| DOI: |
10.1109/JXCDC.2022.3224832 |
| Popis: |
Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit highly beneficial features for nonvolatile memory (NVM) design. Key advantages of VSH-based magnetic random access memory (VSH-MRAM) over spin orbit torque (SOT)-MRAM include access transistor-less compact bit-cell and low-power switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless, large device resistance in the read path ( $R_{S}$ ) due to low mobility of WSe2 and Schottky contacts deteriorates sense margin (SM), offsetting the benefits of VSH-MRAM. To address this limitation, we propose another flavor of VSH-MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower $R_{S}$ in the read path by electrically isolating the read and write terminals. This is enabled by coupling VSH with electrically isolated but magnetically coupled PMA magnets via interlayer exchange coupling. Designing the proposed devices using object-oriented micromagnetic framework (OOMMF) simulation, we ensure the robustness of the exchange-coupled PMA system under process variations. To maintain a compact memory footprint, we share the read access transistor across multiple bit-cells. Compared with the existing VSH-MRAMs, our design achieves 39%–42% and 36%–46% reduction in read time and energy, respectively, along with $1.1\times - 1.3\times $ larger SM at a comparable area. This comes at the cost of $1.7\times $ and $2.0\times $ increase in write time and energy, respectively. Thus, the proposed design is suitable for applications in which reads are more dominant than writes. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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