| Autor: |
Enne Wittenhagen, Patrick James Artz, Philipp Scholz, Friedel Gerfers |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
|
| Zdroj: |
IEEE Open Journal of the Solid-State Circuits Society, Vol 2, Pp 135-143 (2022) |
| Druh dokumentu: |
article |
| ISSN: |
2644-1349 |
| DOI: |
10.1109/OJSSCS.2022.3217019 |
| Popis: |
In this article, a 3-GS/s time-interleaved (TI) RF track-and-hold (TaH) amplifier designed in a 22-nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled front-end (FE) buffer. The measured TaH amplifier has an SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling subsampling. An overall system bandwidth of 4.5 GHz is achieved with an SNR above 55 dBFS. The ultralow-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multitone measurements reveal a third intermodulation and interband nonlinearity with >72 and >82 dBFS, respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode feedback by using the bulk as a control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/−0.8 V supply. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
|
