| Autor: |
Han Xiao, Ruiyong Zhao, Yulan Liu, Yuanzhen Liu, Jing Chen |
| Jazyk: |
angličtina |
| Rok vydání: |
2024 |
| Předmět: |
|
| Zdroj: |
Micromachines, Vol 15, Iss 8, p 1056 (2024) |
| Druh dokumentu: |
article |
| ISSN: |
2072-666X |
| DOI: |
10.3390/mi15081056 |
| Popis: |
The von Neumann architecture is no longer sufficient for handling large-scale data. In-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 °C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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