Enhanced Reliability of a-IGZO TFTs with a Reduced Feature Size and a Clean Etch-Stopper Layer Structure

Autor: Jae-Moon Chung, Fang Wu, Seung-Woo Jeong, Ji-Hoon Kim, Yong Xiang
Jazyk: angličtina
Rok vydání: 2019
Předmět:
Zdroj: Nanoscale Research Letters, Vol 14, Iss 1, Pp 1-10 (2019)
Druh dokumentu: article
ISSN: 1931-7573
1556-276X
DOI: 10.1186/s11671-019-3001-3
Popis: Abstract The effects of diffuse Cu+ in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on the microstructure and performance during a clean etch stopper (CL-ES) process and a back channel etch (BCE) process are investigated and compared. The CL-ES layer formed with a clean component, as verified by TOF-SIMS, can protect the a-IGZO layer from the S/D etchant and prevent Cu+ diffusion, which helps reduce the number of accepter-like defects and improve the reliability of the TFTs. The fabricated CL-ES-structured TFTs have a superior output stability (final I ds/initial I ds = 82.2 %) compared to that of the BCE-structured TFTs (53.5%) because they have a better initial SS value (0.09 V/dec vs 0.46 V/dec), and a better final SS value (0.16 V/dec vs 0.24 V/dec) after the high current stress (HCS) evaluation. In particular, the variation in the threshold voltages has a large difference (3.5 V for the CL-ES TFTs and 7.2 V for the BCE TFTs), which means that the CL-ES-structured TFTs have a higher reliability than the BCE-structured TFTs. Therefore, the CL-ES process is expected to promote the widespread application of a-IGZO technology in the semiconductor industry.
Databáze: Directory of Open Access Journals
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