| Autor: |
Guangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei |
| Jazyk: |
angličtina |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
Sensors, Vol 15, Iss 9, Pp 22509-22529 (2015) |
| Druh dokumentu: |
article |
| ISSN: |
1424-8220 |
| DOI: |
10.3390/s150922509 |
| Popis: |
This paper proposes a real-time feature extraction VLSI architecture for high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed. It increases the system throughput, provides flexibility in image resolution, and offers trade-offs between speed and scaling robustness. The architecture consists of a two-dimensional pipeline array that fully utilizes computational similarities in octaves. Secondly, a substructure (block-serial discrete-time cellular neural network) that can realize a nonlinear filter is proposed. This structure decreases the memory demand through the removal of data dependency. Thirdly, a hardware-friendly descriptor is introduced in order to overcome the hardware design bottleneck through the polar sample pattern; a simplified method to realize rotation invariance is also presented. Finally, the proposed architecture is designed in TSMC 65 nm CMOS technology. The experimental results show a performance of 127 fps in full HD resolution at 200 MHz frequency. The peak performance reaches 181 GOPS and the throughput is double the speed of other state-of-the-art architectures. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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