| Autor: |
Xu Chuanpei, Wang Jifeng, Niu Junhao |
| Jazyk: |
čínština |
| Rok vydání: |
2019 |
| Předmět: |
|
| Zdroj: |
Dianzi Jishu Yingyong, Vol 45, Iss 8, Pp 118-123 (2019) |
| Druh dokumentu: |
article |
| ISSN: |
0258-7998 |
| DOI: |
10.16157/j.issn.0258-7998.190548 |
| Popis: |
The resource network interface is a communication interface that the on-chip network processing unit sends data to the router, and is responsible for packing the data sent by the processing unit into data identified by the routing node. For the high-speed transmission requirements of this interface, this paper uses a combinational logic circuit to design a resource network interface. The communication between the modules in the interface, and the communication between the interface and the processing unit and the routing node are asynchronous communication; the packager in the interface adopts a parity format design, and the cache module adopts the idea of time division multiplexing to reduce the delay of the read and write processes. The interface design is completed in Verilog HDL language and verified on the ModelSim 10.01d platform. The final verification results show that the designed resource network interface can package the data sent by the processing unit into the data identified by the routing node and meet the high-speed data transmission requirements. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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