A CMOS-Compatible Process for ≥3 kV GaN Power HEMTs on 6-inch Sapphire Using In Situ SiN as the Gate Dielectric

Autor: Jie Zhang, Xiangdong Li, Jian Ji, Shuzhen You, Long Chen, Lezhi Wang, Zilan Li, Yue Hao, Jincheng Zhang
Jazyk: angličtina
Rok vydání: 2024
Předmět:
Zdroj: Micromachines, Vol 15, Iss 8, p 1005 (2024)
Druh dokumentu: article
ISSN: 2072-666X
DOI: 10.3390/mi15081005
Popis: The application of GaN HEMTs on silicon substrates in high-voltage environments is significantly limited due to their complex buffer layer structure and the difficulty in controlling wafer warpage. In this work, we successfully fabricated GaN power HEMTs on 6-inch sapphire substrates using a CMOS-compatible process. A 1.5 µm thin GaN buffer layer with excellent uniformity and a 20 nm in situ SiN gate dielectric ensured uniformly distributed VTH and RON across the entire 6-inch wafer. The fabricated devices with an LGD of 30 µm and WG of 36 mm exhibited an RON of 18.06 Ω·mm and an off-state breakdown voltage of over 3 kV. The electrical mapping visualizes the high uniformity of RON and VTH distributed across the whole 6-inch wafer, which is of great significance in promoting the applications of GaN power HEMTs for medium-voltage power electronics in the future.
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