Common mode EMI reduction through PWM methods for three-phase motor controller
| Autor: | Dong Jiang, Jianan Chen, Zewei Shen |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: | |
| Zdroj: | CES Transactions on Electrical Machines and Systems, Vol 3, Iss 2, Pp 133-142 (2019) |
| Druh dokumentu: | article |
| ISSN: | 2096-3564 2837-0325 |
| DOI: | 10.30941/CESTEMS.2019.00019 |
| Popis: | Pulse-width sequences are identified as the determining factor for common-mode (CM) voltage, which together with CM path generate CM current. This paper introduces a series of pulse-width modulation (PWM) methods, which are focusing on reducing CM noise of three-phase inverters as motor controller. Firstly, theoretic analysis and PWM reduction methods of CM voltage for general three-phase two-level inverters are introduced. Analysis results indicate that the realization of CM noise reduction should take switching frequency and loop impedance into consideration together to avoid CM resonant phenomenon. The regular three-phase two-level inverter is incapable of eliminating CM voltage because of the limitation of topology. Then, optimal PWM methods applied to for advanced topologies can be utilized to eliminate the CM voltage theoretically. Two typical typologies presented in this paper are three-level inverters and paralleled inverters. Three-level inverters can achieve zero-CM output voltage by selecting zero-CM voltage vectors at the expense of power quality. However, for paralleled inverters, zero-CM PWM method is able to achieve zero CM voltage output, as well as the improved output current harmonics and voltage balancing. |
| Databáze: | Directory of Open Access Journals |
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