| Autor: |
Shin-Chi Lai, Ying-Hsiu Hung, Yi-Chang Zhu, Szu-Ting Wang, Qi-Xian Huang, Ming-Hwa Sheu, Wen-Ho Juang |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
|
| Zdroj: |
IEEE Access, Vol 10, Pp 79681-79688 (2022) |
| Druh dokumentu: |
article |
| ISSN: |
2169-3536 |
| DOI: |
10.1109/ACCESS.2022.3194261 |
| Popis: |
This study presents a compact $L$ -points discrete cosine transform (DCT) hardware accelerator for $M$ -points Mel-scale Frequency Cepstral Coefficients (MFCC). The main contributions of this work can be summarized as 1) proposing an algorithm with lower complexity; 2) achieving higher accuracy performance; 3) implementing a low-cost accelerator with a unique group of cosine coefficients. For algorithm derivation, the proposed method converts the original formula into the type IV of discrete cosine transform (DCT-IV) with a preprocessing procedure. The kernel computation of DCT-IV can be further derived into the same cosine multiplication with the proposed preprocessing. Therefore, a total of ( $M$ -1) ( $L$ -1) additions, ( $M$ -1) $L$ multiplications, and $L$ coefficients are required for the computation. Compared with Jo et al.’s algorithm, the proposed method respectively reduces the number of additions and multiplications by 42.32 % and 41.67 %. Instead, the number of coefficients is increased by 33.33 %. Moreover, the proposed algorithm exhibits a higher peak signal-to-noise ratio (PSNR) value which is achieved at 90.1dB with a 16-bit coefficient word length. For hardware realization, the FPGA implementation results show that it can operate at a clock rate of 135.85 MHz and requires only 113 combinational elements, 87 registers, 3 DSP multipliers, $64\times 16$ bits RAM and $32\times 16$ bits ROM. Overall, it would be a good choice for integrating MFCC applications in the future. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
|
