| Autor: |
Sang Ho Lee, Jin Park, So Ra Min, Geon Uk Kim, Jaewon Jang, Jin-Hyuk Bae, Sin-Hyung Lee, In Man Kang |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
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| Zdroj: |
Scientific Reports, Vol 12, Iss 1, Pp 1-8 (2022) |
| Druh dokumentu: |
article |
| ISSN: |
2045-2322 |
| DOI: |
10.1038/s41598-022-18682-y |
| Popis: |
Abstract In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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