Redundant Hardware Components for ASIC. RTL Model and Synthesys
| Autor: | Valentin Rozanov, Yuriy Sheynin, Elena Suvorova |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: | |
| Zdroj: | Proceedings of the XXth Conference of Open Innovations Association FRUCT, Vol 426, Iss 22, Pp 378-384 (2018) |
| Druh dokumentu: | article |
| ISSN: | 2305-7254 2343-0737 |
| Popis: | Redundancy is a very popular and effective method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault protection. From hardware design point of view (ASIC design especially) redundancy means area and power increasing. It is very important to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation and additional efforts that need to be done during hardware design flow to get redundant component with fault tolerant mechanism. |
| Databáze: | Directory of Open Access Journals |
| Externí odkaz: |
|