Static Switching Dynamic Buffer Circuit
| Autor: | A. K. Pandey, R. A. Mishra, R. K. Nagaria |
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| Jazyk: | angličtina |
| Rok vydání: | 2013 |
| Předmět: | |
| Zdroj: | Journal of Engineering, Vol 2013 (2013) |
| Druh dokumentu: | article |
| ISSN: | 2314-4904 2314-4912 |
| DOI: | 10.1155/2013/646214 |
| Popis: | We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits. |
| Databáze: | Directory of Open Access Journals |
| Externí odkaz: |
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