| Autor: |
Jae-Hun Lee, Dasom Park, Woojin Cho, Huu Nhan Phan, Cong Luong Nguyen, Jong-Wook Lee |
| Jazyk: |
angličtina |
| Rok vydání: |
2018 |
| Předmět: |
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| Zdroj: |
Sensors, Vol 18, Iss 10, p 3486 (2018) |
| Druh dokumentu: |
article |
| ISSN: |
1424-8220 |
| DOI: |
10.3390/s18103486 |
| Popis: |
Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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