An area‐efficient memory‐based multiplier powering eight parallel multiplications for convolutional neural network processors

Autor:	Seongrim Choi, Suhwan Cho, Byeong‐Gyu Nam
Jazyk:	angličtina
Rok vydání:	2021
Předmět:	Digital circuit design modelling and testing Logic circuits Microprocessors and microcomputers Neural nets (circuit implementations) Semiconductor integrated circuit design layout modelling and testing Logic and switching circuits Electrical engineering. Electronics. Nuclear engineering TK1-9971
Zdroj:	Electronics Letters, Vol 57, Iss 15, Pp 573-575 (2021)
Druh dokumentu:	article
ISSN:	1350-911X 0013-5194
DOI:	10.1049/ell2.12206
Popis:	Abstract Convolutional neural network (CNN) is widely used for various deep learning applications because of its best‐in‐class classification performance. However, CNN needs several multiply‐accumulate (MAC) operations to realize human‐level cognition capabilities. In this regard, an area‐efficient multiplier is essential to integrate a large number of MAC units in a CNN processor. In this letter, we present an area‐efficient memory‐based multiplier targeting CNN processing. The proposed architecture adopts a 32‐port memory shared across eight multiplications. Simulation results show that area is reduced by 18.4% compared with the state‐of‐the‐art memory‐based multiplier.
Databáze:	Directory of Open Access Journals
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