| Autor: |
Hector Daniel Rico-Aniles, Jaime Ramirez-Angulo, Antonio J. Lopez-Martin, Ramon Gonzalez Carvajal, Jose Miguel Rocha-Perez, M. Pilar Garde |
| Jazyk: |
angličtina |
| Rok vydání: |
2020 |
| Předmět: |
|
| Zdroj: |
IEEE Access, Vol 8, Pp 66508-66516 (2020) |
| Druh dokumentu: |
article |
| ISSN: |
2169-3536 |
| DOI: |
10.1109/ACCESS.2020.2985256 |
| Popis: |
A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%. The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the proposed technique. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
|
