Characterization of SOI fabrication process using gated-diode measurements and TEM studies
| Autor: | Jerzy Katcki, Jacek Ratajczak, Andrzej Jakubowski, Lidia Łukasiak, Daniel Tomaszewski, Jan Gibki |
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| Jazyk: | angličtina |
| Rok vydání: | 2000 |
| Předmět: | |
| Zdroj: | Journal of Telecommunications and Information Technology, Iss 3-4 (2000) |
| Druh dokumentu: | article |
| ISSN: | 1509-4553 1899-8852 |
| DOI: | 10.26636/jtit.2000.3-4.24 |
| Popis: | SOI fabrication process was characterized using electrical and TEM methods. The investigated SOI structures included partially and fully depleted capacitors, gated diodes and transistors fabricated on SIMOX substrates. From C-V and I-V measurements of gated diodes, the following parameters of partially depleted structures were determined: doping concentration in both n- and p-type regions, average carrier generation lifetimes in the region under the gate and generation velocity at top and bottom surfaces of the active layer. Structures with short lifetime were studied using a transmission electron microscope. TEM studies indicate that the quality of the active layer in the investigated structures is good. Moreover, these studies were used to verify the thicknesses determined by means of electrical characterization methods. |
| Databáze: | Directory of Open Access Journals |
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