| Autor: |
Esther Lee, Tae Hyeon Kim, Seung Won Lee, Jee Hoon Kim, Jaeun Kim, Tae Gun Jeong, Ji-Hoon Ahn, Byungjin Cho |
| Jazyk: |
angličtina |
| Rok vydání: |
2019 |
| Předmět: |
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| Zdroj: |
Nano Convergence, Vol 6, Iss 1, Pp 1-8 (2019) |
| Druh dokumentu: |
article |
| ISSN: |
2196-5404 |
| DOI: |
10.1186/s40580-019-0194-1 |
| Popis: |
Abstract We have explored the effect of post-annealing on the electrical properties of an indium gallium zinc oxide (IGZO) transistor with an Al2O3 bottom gate dielectric, formed by a sol–gel process. The post-annealed IGZO device demonstrated improved electrical performance in terms of threshold variation, on/off ratio, subthreshold swing, and mobility compared to the non-annealed reference device. Capacitance–voltage measurement confirmed that annealing can lead to enhanced capacitance properties due to reduced charge trapping. Depth profile analysis using X-ray photoelectron spectroscopy proved that percentage of both the oxygen vacancy (VO) and the hydroxyl groups (M–OH) within the IGZO/Al2O3 layers, which serve as a charge trapping source, can be substantially reduced by annealing the fabricated transistor device. Furthermore, the undesired degradation of the contact interface between source/drain electrode and the channel, which mainly concerns VO, can be largely prevented by post-annealing. Thus, the facile annealing process also improves the electrical bias stress stability. This simple post annealing approach provides a strategy for realising better performance and reliability of the solid sol–gel oxide transistor. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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