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Many dynamic random-access memory (DRAM) manufacturing companies encounter significant resistance value deviations during the PVD sputtering process for manufacturing Ti thin films. These resistance values are influenced by the thickness of the thin films. Current mitigation strategies focus on adjusting film thickness to reduce resistance deviations, but this approach affects product structure profile and performance. Additionally, varying Ti thin film thicknesses across different product structures increase manufacturing complexity. This study aims to minimize resistance value deviations across multiple film thicknesses with minimal resource utilization. To achieve this goal, we propose the TSDTM-ANN-GA framework, which integrates the two-stage dynamic Taguchi method (TSDTM), artificial neural networks (ANN), and genetic algorithms (GA). The proposed framework requires significantly fewer experimental resources than traditional full factorial design and grid search method, making it suitable for resource-constrained and low-power computing environments. Our TSDTM-ANN-GA framework successfully identified an optimal production condition configuration for five different Ti thin film thicknesses: Degas temperature = 245 °C, Ar flow = 55 sccm, DC power = 5911 W, and DC power ramp rate = 4009 W/s. The results indicate that the deviation between the resistance values and their design values for the five Ti thin film thicknesses decreased by 86.8%, 94.1%, 95.9%, 98.2%, and 98.8%, respectively. The proposed method effectively reduced resistance deviations for the five Ti thin film thicknesses and simplified manufacturing management, allowing the required design values to be achieved under the same manufacturing conditions. This framework can efficiently operate on resource-limited and low-power computers, achieving the goal of real-time dynamic production parameter adjustments and enabling DRAM manufacturing companies to improve product quality promptly. |
