| Popis: |
The design, analysis, implementation and measurement of an integrated V-band receiver front-end based on $0.15~\mu \text{m}$ GaAs pHEMT process are presented in this paper. The front-end chip uses the super-heterodyne topology which consists of a low noise amplifier, an image reject mixer, and a multiply-by-four ( $\times 4$ ) LO chain. In order to minimize the power consumed by LO chain, an active single-ended mixer is designed which requires extremely low LO power of −5 dBm. Meanwhile, the effect of signal coupling in the integrated chip is analyzed and solutions are proposed. By introducing appropriate filters into the circuit and optimizing the overall layout, the imbalance of in-phase and quadrature signals caused by unwanted coupling can be effectively mitigated, thus enhancing the image rejection of the chip. Probe and module tests are applied to the receiver front-end, and the measurement results reveal that the chip achieves −3 ± 0.7 dB conversion gain, 7 dB noise figure and more than 25 dB image rejection ratio in the RF frequency range of 52–56 GHz. Only one supply voltage of 3 V is required for the chip, and total power consumption is 312 mW. Moreover, with a continuously adjustable phase control of 360° and very broadband IF characteristics, the front-end chip is very suitable for passive millimeter-wave imaging application. |
