| Autor: |
Kouhei Toyotaka, Yuto Yakubo, Kazuma Furutani, Haruki Katagiri, Masashi Fujita, Yoshinori Ando, Toru Nakura, Shunpei Yamazaki |
| Jazyk: |
angličtina |
| Rok vydání: |
2024 |
| Předmět: |
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| Zdroj: |
IEEE Journal of the Electron Devices Society, Vol 12, Pp 486-494 (2024) |
| Druh dokumentu: |
article |
| ISSN: |
2168-6734 |
| DOI: |
10.1109/JEDS.2024.3418036 |
| Popis: |
Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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