| Autor: |
Seyed Navid Mousavi, Fengping Chen, Mahdi Abbasi, Mohammad R. Khosravi, Milad Rafiee |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
|
| Zdroj: |
Digital Communications and Networks, Vol 8, Iss 4, Pp 561-575 (2022) |
| Druh dokumentu: |
article |
| ISSN: |
2352-8648 |
| DOI: |
10.1016/j.dcan.2022.04.010 |
| Popis: |
The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things (IoT). In recent years, researchers have tried to develop hardware-based solutions for the classification of Internet packets. Due to higher throughput and shorter delays, these solutions are considered as a major key to improving the quality of services. Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput. The proposed architectures, however, cannot reach a compromise among power consumption, memory usage, and throughput rate. In view of this, the architecture proposed in this paper contains a pipeline-based micro-core that is used in network processors to classify packets. To this end, three architectures have been implemented using the proposed micro-core. The first architecture performs parallel classification based on header fields. The second one classifies packets in a serial manner. The last architecture is the pipeline-based classifier, which can increase performance by nine times. The proposed architectures have been implemented on an FPGA chip. The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput. The architecture has a power consumption of is 1.294w, and its throughput with a frequency of 233 MHz exceeds 147 Gbps. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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