| Autor: |
Ram Sharma Nitesh, Jagadheswaran Rajendran, Harikrishnan Ramiah, Binboga Siddik Yarman |
| Jazyk: |
angličtina |
| Rok vydání: |
2019 |
| Předmět: |
|
| Zdroj: |
IEEE Access, Vol 7, Pp 158808-158819 (2019) |
| Druh dokumentu: |
article |
| ISSN: |
2169-3536 |
| DOI: |
10.1109/ACCESS.2019.2949369 |
| Popis: |
This paper presents a comprehensive design of a fully integrated multistage GaAs HBT power amplifier that achieves both linearity and high efficiency within a chip area of 0.855 mm2 for 4G and 5G applications covering the lower frequency band of 700-800 MHz. A novel linearizer circuit is integrated to a dual stage class-AB PA to minimize the AM-PM (Amplitude Modulation-Phase Modulation) distortion generated by the parasitic capacitance at the PN-junction under low bias current condition. The linearized power amplifier is able to operate within a 100 MHz linear operating bandwidth (700-800 MHz) while meeting the adjacent channel leakage ratio (ACLR) specification for 4G and 5G application. The fully integrated PA achieves a wideband efficiency of 57.5% at 28.5 dBm output power. Observing a respective input and output return losses of less than 13 dB and 10 dB, the PA delivers a power gain within the range of 34.0-37.0 dB across the operating bandwidth while exhibiting an unconditional stability characteristic from DC up to 5 GHz. The proposed linearization method paves the way of reducing the complexity of linear and high efficiency PA design which is associated with complicated and high-power consumption linearization schemes. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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