ADC Emulation on FPGA
| Autor: | Huma Tabassum, Krishna Prathik BV, Sujatha S Hiremath |
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| Jazyk: | angličtina |
| Rok vydání: | 2023 |
| Předmět: | |
| Zdroj: | International Journal of Electronics and Telecommunications, Vol vol. 69, Iss No 3, Pp 425-430 (2023) |
| Druh dokumentu: | article |
| ISSN: | 2081-8491 2300-1933 |
| DOI: | 10.24425/ijet.2023.144379 |
| Popis: | Analog-to-Digital Converters (ADCs) are devices that transform analog signals into digital signals and are used in various applications such as audio recording, data acquisition, and measurement systems [1]. Prior to the development of actual chip, there is a need for prototyping, testing and verifying the performance of ADCs in different scenarios. Analog macros cannot be tested on an FPGA. In order to ensure the macros function properly, the emulation of the ADC is done first. This is a digital module and can be designed in System Verilog. This paper demonstrates the design of the module on FPGA for Analog to Digital Converter (ADC) emulation. The emulation is done specific to the ADC macro which has programmable resolutions of 12/10/8/6 bit. |
| Databáze: | Directory of Open Access Journals |
| Externí odkaz: |
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