| Autor: |
Ya-Chi Huang, Meng-Hsueh Chiang, Shui-Jinn Wang, Jerry G. Fossum |
| Jazyk: |
angličtina |
| Rok vydání: |
2017 |
| Předmět: |
|
| Zdroj: |
IEEE Journal of the Electron Devices Society, Vol 5, Iss 3, Pp 164-169 (2017) |
| Druh dokumentu: |
article |
| ISSN: |
2168-6734 |
| DOI: |
10.1109/JEDS.2017.2689738 |
| Popis: |
Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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