| Autor: |
Li Jiamin, Dai Zibin, Wang Yiwei |
| Jazyk: |
čínština |
| Rok vydání: |
2018 |
| Předmět: |
|
| Zdroj: |
Dianzi Jishu Yingyong, Vol 44, Iss 1, Pp 28-32 (2018) |
| Druh dokumentu: |
article |
| ISSN: |
0258-7998 |
| DOI: |
10.16157/j.issn.0258-7998.172194 |
| Popis: |
Modular multiplication, addition and subtraction are frequently used in ECC as the key operations. It has been an research hotspot that how to implement modular operations high-effciently and low-costly. Researching on Montgomery modular multiplication of FIOS, and modular add-sub, and combined with reconfigurable technology, this paper implemented an length scalable MAS(multiplication-addition-subtraction) which support the operation in both finite field and prime field. This MAS is descript by Verilog HDL, and it was integrated in CMOS 0.18 μm technology library. Circuit maximum clock frequency is 230 MHz. This architecture not only has advantages in the speed and area, but also can flexibly achieve operations of different length. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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