Computational methods to increase the speed of FPGA-based discrete wavelet transforms
| Autor: | Sergey V. Sai, Alexey V. Zinkevich |
|---|---|
| Jazyk: | English<br />Russian |
| Rok vydání: | 2023 |
| Předmět: | |
| Zdroj: | Naučno-tehničeskij Vestnik Informacionnyh Tehnologij, Mehaniki i Optiki, Vol 23, Iss 1, Pp 79-87 (2023) |
| Druh dokumentu: | article |
| ISSN: | 2226-1494 2500-0373 |
| DOI: | 10.17586/2226-1494-2023-23-1-79-87 |
| Popis: | The article considers the computational methods and features of the construction of a complex functional block for the implementation of the discrete wavelet transform (DWT) Dobeshie 9/7 in digital image signal processing systems based on FPGA. We proposed a mathematical model and algorithms for the implementation of parallel and series-convector methods of signal processing to calculate the coefficients of a discrete bi-orthogonal Dobeshie wavelet 9/7 taking into account the architecture of used FPGA. The model is based on wavelet transform factorization methods using lifting schemes. In contrast to conventional lifting schemes, the proposed method and algorithms can increase the speed of FPGA calculations with simplified hardware implementation. CAD Quartus II and ModelSim are used as a development environment. The behavioral model is written in Verilog HDL. Altera Cyclone® IV 4CE115 was used as FPGA. On the basis of the obtained behavioral model the testing module was developed and the simulation of digital circuit in the ModelSim environment was carried out. The formula for estimating the number of clock cycles of the forward and reverse DWT has been proposed; on its basis the estimate of the number of parallel computations depending on the number of input elements and the characteristics of the FPGA was obtained. As a result of experiments the dependences of the number of cycles for DWT computation depending on the size of the side of a square image with different variants of the number of parallel processing blocks were obtained. It is shown that parallel work of several independent modules gives a possibility to conduct concurrent processing of several input columns (rows) from input 2D array, and unification of the multiplier-summing module allows to increase efficiency of calculations and to reduce volume of occupied hardware resources. Conveyor based DWT structure is characterized by less hardware costs in terms of implementation of the calculator unit and memory allocation. As a result of testing the digital circuit, it was found that the developed block structure can significantly increase the DWT speed as well as reduce the cost of the system on a chip. The proposed realization of the block of two-dimensional forward and reverse wavelet transform for the Dobeshi 9/7 filter bank forms a complete module and can be used as a ready-made complex functional block for further development of high quality image transmission systems in real time. |
| Databáze: | Directory of Open Access Journals |
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