500 MS/s 4-Bit Flash ADC with Complementary Architecture
| Autor: | Hyun-Yeop Lee, Eun-Ho Song, Yun-Seong Eo, Choon-Sik Cho, Young-Jin Kim |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2024 |
| Předmět: | |
| Zdroj: | Journal of Electromagnetic Engineering and Science, Vol 24, Iss 1, Pp 98-107 (2024) |
| Druh dokumentu: | article |
| ISSN: | 2671-7255 2671-7263 |
| DOI: | 10.26866/jees.2024.1.r.209 |
| Popis: | This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 Vpp operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and preamp circuits corresponding to the analog stages are designed using complementary architecture to attain a sufficient swing range even at a low supply voltage. Notably, the proposed structure satisfies the error requirements. The error source of the flash ADC, such as the comparator’s input referred offset, did not degrade its performance, while the use of a calibration circuit, characterized by power consumption and area burdens and increased complexity, could also be avoided. Therefore, the proposed flash ADC met the error requirements, such as the comparator’s input referred offset, without the need for calibration circuits. The chip, fabricated using the TSMC 65 nm process, covers an area of 1,160 × 950 μm2 and consumes 78 mW of power. Furthermore, its signal-to-noise and distortion ratio and spurious-free dynamic range were measured to be 23.36 dB and 30.26 dB, respectively, at a sampling frequency of 500 MHz. |
| Databáze: | Directory of Open Access Journals |
| Externí odkaz: |
|